The project as a whole was a success. The final working processor was downloaded onto a Xilinx FPGA and ran original PDP-8 machine code. Any program written using the PDP-8 assembler, explained in the previous section, could be run on the new processor.

In addition to the processor being instruction set compatible with the original PDP-8, it also needed to take advantage of modern technology. The use of a larger transistor budget has enabled the processor to outperform the original design. The improvement isn’t solely due to the technology being faster, but also better use of the available technology. Most of the improvements in functional speed increase are achieved by the reduction of states in the state model. It has shown that by making subtle changes to the arrangement of function blocks the processor performance can be increased.

Choosing to make the top level a hand drawn schematic was the most important decision made in the project. This allowed the processor to be tested with great efficiency. The flow of data could be seen easily with each clock cycle. Seeing this flow allowed the data paths to be used more efficiently and increase parallelism.

The processor would be much more useful had the I/O interface been implemented. Due to time restrictions this was not possible. This could be added as a module had time permitted. An I/O interface would allow the rest of the instruction set to be used and programs such as FOCAL, a basic language, to be run.

The project has also shown that without the development in tools, such as Powerview, the desktop development of a processor would not be possible. Using VHDL means that different implementations can be tested and compared with each other before one idea is fixed into the design. This is further aided by the ability to design and test a processor as a set of modules, where each can be simulated individually.

If this project were extended, or taken on by a student in future years, there are a number of areas for development. The initial aim would be to fully implement the I/O class of instructions and complete the interface. Another suggested development is to attach the FPGA processor to the back plane of an original PDP-8 unit.

Personally this project has given me a great insight into the design of a microprocessor. During the development cycle there were times when the entire design looked flawed. Solving these problems gave me great satisfaction.