A FGPA Implementation of the PDP-8

Project Aim:

To implement a PDP-8 compatible processor into a Xilinx 4000 Series FPGA (Field Programmable Gate Array). I am doing this implementation a Final Year Project for my Computer Engineering Degree at The University of Manchester in the UK.

Current Status:

The design in now running real PDP8 code at a speed of 5 MHz. This means that a TAD instruction will execute in 60ns. The refined state model means that all instructions complete under 100ns (for a skip instruction). Also all microcoded instruction run at 80ns, independent of the number of microcodes in that instruction.

VHDL

Click here for a complete list of my VHDL code. I'll try to keep it as maintained as possible
You are free to use the code as you like, as long as it is only for personal use.


Final Report

This is my final report for the project
E-mail: Jon Andrews