A FGPA Implementation of the PDP-8
To implement a PDP-8 compatible processor into a Xilinx 4000 Series FPGA (Field Programmable Gate Array).
I am doing this implementation a Final Year Project for my Computer Engineering Degree at The University of Manchester in the UK.
The design in now running real PDP8 code at a speed of 5 MHz. This means that a TAD instruction will execute in
60ns. The refined state model means that all instructions complete under 100ns (for a skip instruction). Also all
microcoded instruction run at 80ns, independent of the number of microcodes in that instruction.
- Instruction Format and Decode Ready
- Datapath Complete
- State Machine reduced to 5 states from 13, Click here the diagram
- ALU currently being written in VHDL
- Powerpoint Presentation
- Schematic for top level design to-date (Now in Postscript)
- Auto-Index state removed, this value is now calculated as part of the indirect path and then used conditionally
- Microcoded Instructions now fit into existing 4 states and don't require looping in E0
- Control Draft Made
- TAD Z and TAD I Instructions executed sucessfully.
- Instructions Complete The fully basic instruction set is working.
- Problems found in VHDL Coding...Validation undertaken
- All VHDL Synthesized to gates
- Running on FPGA Array
- Next stage, get I/O working.
Click here for a complete list of my VHDL code. I'll try to keep it as maintained as possible
You are free to use the code as you like, as long as it is only for personal use.
This is my final report for the project